scLLptr

Announcing my upcoming C DSP sin/cos turn lib: 4 accuracy classes Perfect sin odd / cos even symmetry Full sweep output sum is 0 Quarter points exact: 0 and ±(2^OUT − 1) Strictly monotonic in between Selectable Q1.31 to Q25.7 output No LUT, no FPU⬇️

Wordle 1,949 6/6 ⬜⬜⬜⬜⬜ ⬜🟨🟨⬜⬜ ⬜🟩🟩🟩🟩 ⬜🟩🟩🟩🟩 ⬜🟩🟩🟩🟩 🟩🟩🟩🟩🟩 Daily Duotrigordle #1693 Guesses: 36/37 0️⃣9️⃣ 1️⃣0️⃣ 2️⃣8️⃣ 2️⃣1️⃣ 1️⃣4️⃣ 2️⃣2️⃣ 2️⃣9️⃣ 2️⃣3️⃣ 1️⃣5️⃣ 1️⃣6️⃣ 3️⃣0️⃣ 3️⃣1️⃣ 2️⃣4️⃣ 0️⃣3️⃣ 1️⃣1️⃣ 2️⃣5️⃣ 3️⃣4️⃣ 1️⃣7️⃣ 1️⃣3️⃣ 2️⃣6️⃣ 1️⃣8️⃣ 3️⃣5️⃣ 3️⃣2️⃣ 0️⃣7️⃣ 3️⃣6️⃣ 1️⃣9️⃣ 3️⃣3️⃣ 0️⃣8️⃣ 0️⃣5️⃣ 2️⃣7️⃣ 0️⃣4️⃣ 2️⃣0️⃣

Wordle 1,933 5/6 🟨⬜⬜⬜⬜ ⬜⬜⬜🟩⬜ ⬜🟨⬜🟩⬜ ⬜⬜🟩🟩🟩 🟩🟩🟩🟩🟩

There's no limit in optimizing <30 int math instruction code. Lowered abs error below 2.0 ULP. 30+ useful bits. For refwrence, float mantissa is 24 bit. To think of megabytes of bloat fat abstraction layers add to modern software, making it much slower. Releasing the lib once i perfect it.

I really enjoy pushing the M33 to the limits. Latest result for int32_t sin_q1_31(uint32_t phase_q0_32): max abs error ±2.95 ULP, at 27-32 cy/loop, using 7 to 4 regs, respectively. Absolute error-wise, 21x more precise than ideal float sinf, and up to 5x faster. No FPU, tables, time-deterministic

Smallest error I got for sin Q1.31 approximation is 1.42 × 10⁻⁹ or ±3.05 ULP. Four optimization classes, balance speed vs reg pressure, measured: >loop : 32 cy/loop (7 regs , 3 exposed for hoisting) >perf : 32 cy/loop (6 * , 2 *) >baln : 35 cy/loop (5 * , 1 *) >sngl : 37 cy/loop (4 * , 0 *)

Wordle 1,923 3/6 ⬜⬜⬜⬜⬜ 🟩🟩⬜⬜🟩 🟩🟩🟩🟩🟩 Daily Duotrigordle #1667 Guesses: 35/37 0️⃣9️⃣ 0️⃣8️⃣ 2️⃣9️⃣ 1️⃣7️⃣ 1️⃣2️⃣ 1️⃣1️⃣ 0️⃣7️⃣ 3️⃣3️⃣ 1️⃣8️⃣ 1️⃣0️⃣ 0️⃣5️⃣ 2️⃣3️⃣ 1️⃣6️⃣ 3️⃣2️⃣ 2️⃣1️⃣ 0️⃣3️⃣ 2️⃣2️⃣ 1️⃣9️⃣ 1️⃣4️⃣ 3️⃣1️⃣ 2️⃣8️⃣ 3️⃣4️⃣ 2️⃣4️⃣ 0️⃣4️⃣ 2️⃣7️⃣ 3️⃣0️⃣ 2️⃣0️⃣ 2️⃣5️⃣ 0️⃣6️⃣ 1️⃣3️⃣ 2️⃣6️⃣ 3️⃣5️⃣

Working on a fast sin/cos lib for RP2350. Reached: int32_t sin_q1_31(uint32_t phase_q0_32) Full input range sweep: worst abs err = -1.512730e-09, SFDR = -176.40 dBc, at phase 4262742563. No LUTs. No FPU. Time deterministic. No branching. 32 ASM instructions/35 cycles.

Wordle 1,893 5/6 ⬜⬜⬜🟨⬜ ⬜⬜⬜🟩⬜ ⬜⬜🟩🟩⬜ ⬜🟩🟩🟩🟩 🟩🟩🟩🟩🟩 Daily Duotrigordle #1637 Guesses: 37/37 1️⃣3️⃣ 3️⃣7️⃣ 1️⃣4️⃣ 1️⃣5️⃣ 2️⃣4️⃣ 2️⃣5️⃣ 2️⃣6️⃣ 3️⃣5️⃣ 1️⃣6️⃣ 0️⃣8️⃣ 1️⃣9️⃣ 2️⃣0️⃣ 2️⃣1️⃣ 2️⃣2️⃣ 3️⃣6️⃣ 2️⃣7️⃣ 0️⃣9️⃣ 1️⃣0️⃣ 2️⃣8️⃣ 1️⃣7️⃣ 2️⃣9️⃣ 3️⃣0️⃣ 0️⃣3️⃣ 3️⃣1️⃣ 0️⃣7️⃣ 0️⃣4️⃣ 3️⃣2️⃣ 3️⃣3️⃣ 2️⃣3️⃣ 1️⃣8️⃣ 3️⃣4️⃣ 1️⃣2️⃣

Final #m33 #rp2350 #pico2 fast gamma lut calc optimization: * Gamma integer input: 1000 to 3000 (exact 1/1000 steps) * 8b to 16b: 23 instr/2 entries (Max err 0/+1 LSB) * 8b to max 23b: 22 instr/2 entries (Max err -18/+20 LSB for 23b, ~halves for each bit down) (Both plus loop overhead - 2 instr)

Accuracy test runs against libc's pow().

Wordle 1,890 5/6 🟨⬜⬜⬜⬜ ⬜⬜🟨⬜⬜ 🟨🟨⬜⬜⬜ ⬜🟩🟩🟨⬜ 🟩🟩🟩🟩🟩 Daily Duotrigordle #1634 Guesses: 37/37 0️⃣6️⃣ 2️⃣8️⃣ 1️⃣7️⃣ 2️⃣9️⃣ 3️⃣0️⃣ 1️⃣8️⃣ 0️⃣3️⃣ 3️⃣1️⃣ 1️⃣2️⃣ 1️⃣9️⃣ 0️⃣7️⃣ 2️⃣0️⃣ 3️⃣2️⃣ 3️⃣3️⃣ 0️⃣5️⃣ 2️⃣1️⃣ 3️⃣6️⃣ 3️⃣7️⃣ 3️⃣4️⃣ 1️⃣3️⃣ 3️⃣5️⃣ 1️⃣5️⃣ 2️⃣2️⃣ 0️⃣8️⃣ 0️⃣9️⃣ 2️⃣3️⃣ 1️⃣1️⃣ 2️⃣4️⃣ 2️⃣5️⃣ 2️⃣6️⃣ 1️⃣6️⃣ 2️⃣7️⃣

Gamma LUT calculation optimized for ARM Cortex-M33 #RP2350 #Pico2. 256-entry, 16-bit output LUT. 29 instr / 30 cycles per 2 entries (interleaved to mask latency). Targeted range γ = 1.000…3.000 in 0.001 steps. Maximum error: 0…+1 LSB over entire specified range. Error explodes outside ROI.

Intermittently working on the HUB75 RP2350 solution. Updated project name is secret for now. It'll be a 100% ASM solution with a highly modular and extensible arch, and a rich set of compile-time switches. Everything is dynamically reconfigurable at runtime, aside from single-shot HW interface setup

I highly recommend this series www.youtube.com/watch?v=GVjc... as well as all other videos from this channel.

Quick test of a 140W PD3.1 power bank module based on IP2366. Fnirsi HS-02B iron can run on a Parkside X20V 4Ah battery for 8+hrs under normal conditions. Same system can charge a notebook or a phone. Todo: ▶️Tap into battery's charger signaling port and battery MCU's UART. ▶️Control IP2366 via I2C.

75% done with #rp2350_hub75_agp - 95% in ASM. Added P4 support and checkerboard dithering on the lower planes. Planning P8 bank shifting (top 32/64/128 entries). Goals: ▶️Full runtime config within compile-time limits ▶️Compile-time switches for FW size / RAM optimization + RAM vs FLASH code execution

Scientists Built Tiny, Portable Atomic Clocks—and Naturally, They’re Headed for Drones gizmodo.com/scientists-b...

​Out with the old, in with the new! Left-2024 Pico 1 based test board, right-2026 RP2350B WeAct based test board. Didn't pay attention to RGB pin orientation, so I added HUB75_SWAP_RGB_BGR & HUB75_SWAP_PX0_PX1 compile-time switches. Bake right into the ASM with zero runtime cost. #rp2350_hub75_agp

​No home remodeling this weekend. Cut the tips of two fingers. Healing time. Hoping I can still solder the last VHCT541 and see the first animations. #rp2350_hub75_agp went through multiple iterations for a beautiful design, on paper. I skipped "first make it work, then make it pretty".

o> so grateful www.youtube.com/watch?v=2sYF...

I've been working on #rp2350_hub75_agp on & off. Updated goals: ▶️User registered P8//RGB332/565/888 oversized panning buffer ▶️No 2x buffer. Single 1/8 frame PIO DMA buffer ▶️ASM pipeline with 12-bit gamma expansion faster than PIO DMA per row ▶️Core 1 max utilization, Core 0 free Hope it works out.

Storm shutters operative

I took a couple of days off to work on my HUB75 driver project. As if. Actually, my other dwelling kitchen and bathroom renovation project. Sure beats coding. Perfect level!

Help is always appreciated

A competent manager. What a rare breed. youtube.com/shorts/GIxnV...

Better hobby than coding. .

Hats off to Marposs for the on-board spare fuse.

Finally

I set goals for my RP2350 HUB75 driver project: ▶️13-bit/col render buffer ▶️2 cascaded PIOs + 2x frame buffer ▶️BCM, also bottom 3 bitplanes PWMed ▶️ASM parallel 4x4px RGB-shuffling on Core 1 ▶️Vsync + Active FB outputs ▶️DMA interrupt-free ▶️0 CPU cost for static output #RP2350 #Embedded #HUB75

Alas. RP2350 ✅ HUB75 ✅panels. Level shifters ❎. Found some VHCT541s locally, ordering, but the week starts with a 2-day national holiday. Extruding photons next weekend. 🤷‍♂️🛠️ P.S. Another idea, to sacrifice one GPIO (RP2350B has 48) for VSync.

Built a RP2040 HUB75 driver 2yrs ago: 2 chans, 2x buffering, and 8-10bit BCM via a single DMA stream to 2 cascaded PIO engines. 7+3 PIO instr. It was a naive try. Starting fresh with RP2350. Simplifying RGB engine and refining control engine to PWM lower bitplanes, to address the min on-time issue.