Julien F

BridgeBench.ai managed to have a go at Fable 5 before it was taken down. Behind the artificially over inflated hype and people losing their mind for the 100th time this year, it confirms what I experienced : it’s the exact same shit, now 3 times the price

There’s a very simple reason everyone, every time, think the next model is revolutionary : you treat it like a benchmark, asking things that you already know how to compare against, like you did with every model before that blew your mind. This is the honeymoon phase, over and over again.

That’s it, I did it ! I designed a fully functional RV32I RISC-V pipelined (!!) processor. What an endeavor it has been 😭 It can run at 55MHz on the DE10-Lite. Thanks to everyone that made this achievement possible ! Stay tuned for more FPGAs shenanigans ! #riscv #iot #fpga

Welp… I started an #opensource, kind of #osh thing. 🧑‍💻 I’m designing a RISC-V 6 steps pipeline CPU core, synthesizable on real hardware. Once the core supports the full RV32I instruction set (bare metal, no CSRs), I’ll add some IO, timers, and turn it into an MCU. I’m impatient to show it to you !

Today’s goal is to implement data and control hazard handling LW is the main challenge here, the registered BRAM of the FPGA hardware forces me to implement an FSM to deal with the extra latency, and I need to stall all the pipeline except the writeback stage, not just the « upstream » stages.

Welp… I started an #opensource, kind of #osh thing. 🧑‍💻 I’m designing a RISC-V 6 steps pipeline CPU core, synthesizable on real hardware. Once the core supports the full RV32I instruction set (bare metal, no CSRs), I’ll add some IO, timers, and turn it into an MCU. I’m impatient to show it to you !

Today’s goal is to implement data and control hazard handling LW is the main challenge here, the registered BRAM of the FPGA hardware forces me to implement an FSM to deal with the extra latency, and I need to stall all the pipeline except the writeback stage, not just the « upstream » stages.

Welp… I started an #opensource, kind of #osh thing. 🧑‍💻 I’m designing a RISC-V 6 steps pipeline CPU core, synthesizable on real hardware. Once the core supports the full RV32I instruction set (bare metal, no CSRs), I’ll add some IO, timers, and turn it into an MCU. I’m impatient to show it to you !

Welp… that escalated quickly 😅

I promised more FPGA shenanigans. What about a custom RISC-V cpu that can run C code ? I’ve designed a primitive single cycle RV32Ish (it’s missing a few instr) CPU and implemented it on the DE10-Lite. It broke me 😂 What a journey it has been from the @shawnhymel.bsky.social FPGA course to this !

Adding new instructions has reached a diminishing return point, I think I’m ready to move on my first viable architecture : multi cycle cpus. Single cycle processors are great to understand what a datapath and a control unit is, but it’s impossible to interface with complex devices. I’m so pumped!

I promised more FPGA shenanigans. What about a custom RISC-V cpu that can run C code ? I’ve designed a primitive single cycle RV32Ish (it’s missing a few instr) CPU and implemented it on the DE10-Lite. It broke me 😂 What a journey it has been from the @shawnhymel.bsky.social FPGA course to this !

Here’s the c code it runs. I compiled it using a custom linker script and disassembled the .text section to copy the instructions words. Put it into a $readmemh to put in into « ram » (Quartus is not inferring RAM because of the combinational read, it’s using flip flops 😂)

Revision 2 of my Nixie Tube power supply is now in production. It’s rated for 6 IN-14 tubes @ 2mA, and works with either an USB-C PD 3.0 3A input or a direct 15VDC pin header. I’ll open source the final revision once I’m sure it does not blow up and everything is fine #oshw #opensource #nixie

I think I settled on something for my « endgame » side project : A Nixie Tube clock based on a custom RISC-V processor implemented on an FPGA, running custom C code. It combines every aspect of Digital Design and Computer Architecture, plus it’s a fun project. Here’s the power supply! (cont)

Please note the botched diode 😂. What I wanted with this one was to design a high voltage flyback converter from scratch. I think I can downsize multiple component a fair bit but nailing the first revision (minus the diode) is already quite a miracle ! Voltage is quite high due to resistor values

Puzzled about the @frame.work event! On one hand, awesome work with the 13, which is now a mature piece of hardware with valuable updates. Then the 12… wwwokay I guess ? A modular touchscreen 2in1 is fire 🔥, but the bezels 😬 Then the mindf*ck begins (cont…)

I understand the « let’s put this cool chip somewhere », but the desktop is a miss for me. That’s a desktop less modular than a desktop 🤷‍♂️. And… now… the ugly… what the hell with the 16 guys ? I know you probably have something for later, but you’re pulling a Nintendo on us, not announcing it…

Continuing my learning journey! Writing dirty HDL code is already far from easy, but writing clean HDL is way harder ! Reading the amazing book "Digital Design and Computer Architecture" by Sarah and David Harris, I decided to implement in hardware one of the examples, the traffic light controller.

I've uploaded the code to GH if you're curious. It's not that good or impressive, but I wanted to document my learning journey github.com/julienfdev/s...

Continuing my learning journey! Writing dirty HDL code is already far from easy, but writing clean HDL is way harder ! Reading the amazing book "Digital Design and Computer Architecture" by Sarah and David Harris, I decided to implement in hardware one of the examples, the traffic light controller.

The book shows how to write self-testing benches, it's way easier than forcing signals in Modelsim! I've learned a lot writing testbenches for this project and others exercises! I also learnt that HDL that can be simulated won't necessarily synthesize, this was new !

Continuing my learning journey! Writing dirty HDL code is already far from easy, but writing clean HDL is way harder ! Reading the amazing book "Digital Design and Computer Architecture" by Sarah and David Harris, I decided to implement in hardware one of the examples, the traffic light controller.