The last month of my life: BreakingTTAPs This is a custom transport-triggered, 32 bit processor that will be fabricated by GlobalFoundries on their 180nm process (via of wafer.space) I'll make a video at some point, but some high level details here:
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- Transport-triggered architecture - ~20Mhz - Two 32 bit data buses (i.e. two instructions per cycle) - 1024 double slot instruction memory - 256 word stack - 4kb of general RAM - 80 or so various instruction types - 16 GPIO, SPI, UART, 8 bit parallel memory loader interface
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Chip was written in Spade HDL (spade-lang.org), which transpiles down to SystemVerilog. That's then fed into a LibreLane build process that turns the verilog into transistors. All open source!
spade-lang.org
Spade | Spade Hardware Description Language