Post

- Transport-triggered architecture - ~20Mhz - Two 32 bit data buses (i.e. two instructions per cycle) - 1024 double slot instruction memory - 256 word stack - 4kb of general RAM - 80 or so various instruction types - 16 GPIO, SPI, UART, 8 bit parallel memory loader interface

I did manage to sneak in two small silicon art logos. Wish I had more time to put more on the chip but oh well!

Clock speed is sorta up in the air. Still optimizing, but simulations say it should hit ~20MHz in all "process corners" (i.e. if the fab makes slow transistors and the chip is 125C hot). Probably faster in nominal case but we'll see